VHDL Implementation and Codeing of 2-bit Vedic Multiplier

Sangeet Lyrics 7:18 PM

Sangeet Lyrics

The basic Gate level Diagram and More General Diagram Can be drawn as shown Below with some blocks:-

Code for 2-bit Vedic Multiplier is shown Below:-

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-- Company: VHDL Language
-- Engineer: Manohar Mohanta
--
-- Create Date: 20:17:34 12/25/2016
-- Design Name: Vedic Multiplier
-- Module Name: Vedic_Multiplier_2bits - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Vedic_Multiplier_2bits is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
c : out STD_LOGIC_VECTOR (3 downto 0));
end Vedic_Multiplier_2bits;

architecture Behavioral of Vedic_Multiplier_2bits is

signal s1: STD_LOGIC;
signal s2: STD_LOGIC;
signal s3: STD_LOGIC;
signal s4: STD_LOGIC;

begin
c(0)<= a(0) and b(0);
s1<=a(1) and b(0);
s2<= a(0) and b(1);
c(1)<= s1 xor s2;
s3<= s1 and s2;
s4<= a(1) and b(1);
c(2)<= s3 xor s4;
c(3)<= s3 and s4;
end Behavioral;