VHDL Implementation and Coding of 8-bit Vedic Multiplier

To implement 4-bit Vedic Multiplier we require the following Sub-blocks:

1. 4-bit Vedic Multiplier
2. 8-bit Adder
     2(a).Full Adder.
     2(b). Half Adder.
3.12-bit Adder
     3(a).Full Adder.
     3(b). Half Adder.

So if you are visiting first time to my page them once have a look on the above codes also.Then you can have better understanding.

The Block Diagram of 8-Bit Vedic Multiplier

Code for 8-bit Vedic Multiplier is shown Below:-

----------------------------------------------------------------------------------

-- Company: VHDL Language

-- Engineer: Manohar Mohanta

-- 

-- Create Date:    11:47:40 01/03/2017 

-- Design Name:    Multiplier

-- Module Name:    Vedic_Multiplier_8bit - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Vedic_Multiplier_8bit is

    Port ( a : in  STD_LOGIC_VECTOR (7 downto 0);

           b : in  STD_LOGIC_VECTOR (7 downto 0);

           c : out  STD_LOGIC_VECTOR (15 downto 0));

end Vedic_Multiplier_8bit;

architecture Behavioral of Vedic_Multiplier_8bit is

signal s: STD_LOGIC_VECTOR(7 downto 0);signal s1: STD_LOGIC_VECTOR(7 downto 0);

signal s2: STD_LOGIC_VECTOR(7 downto 0);signal s3: STD_LOGIC_VECTOR(7 downto 0);

signal s4: STD_LOGIC_VECTOR(7 downto 0);signal s5: STD_LOGIC_VECTOR(8 downto 0);

signal s6: STD_LOGIC_VECTOR(11 downto 0);signal s7: STD_LOGIC_VECTOR(11 downto 0);

signal s8: STD_LOGIC_VECTOR(11 downto 0);signal s9: STD_LOGIC_VECTOR(11 downto 0);

begin

Vedic_Multiplier_4bit_1:entity work.Vedic_Multiplier_4bit

port map( a =>a(3 downto 0),b =>b(3 downto 0),c=>s);

Vedic_Multiplier_4bit_2:entity work.Vedic_Multiplier_4bit

port map( a =>a(7 downto 4),b =>b(3 downto 0),c=>s1);

Vedic_Multiplier_4bit_3:entity work.Vedic_Multiplier_4bit

port map( a =>a(3 downto 0),b =>b(7 downto 4),c=>s2);

Vedic_Multiplier_4bit_4:entity work.Vedic_Multiplier_4bit

port map( a =>a(7 downto 4),b =>b(7 downto 4),c=>s3);

c(3 downto 0)<= s(3 downto 0);

s4<=("0000"&s(7 downto 4));

Adder_8bit:entity work.Adder_8bit

port map(a=>s1,b=>s4,s=>s5(7 downto 0),c=>s5(8));

s6<=("0000"&s2(7 downto 0));s7<=(s3(7 downto 0)&"0000");

Adder_12bit:entity work.Adder_12bit

port map(a=>s6(11 downto 0),b=>s7,s=>s8(11 downto 0));

s9<=("0000"&s5(7 downto 0));

Adder_12bit_1:entity work.Adder_12bit

port map(a=>s9,b=>s8,s=>c(15 downto 4));

end Behavioral;

Below is the Video Explaining The Concept:-

• Twitter
• Facebook
• Google
• Tumblr
• Pinterest