VHDL Implementation and Coding of 4-bit Vedic Multiplier

To implement 4-bit Vedic Multiplier we require the following Sub-blocks:

1. 2-bit Vedic Multiplier
2. 4-bit Adder
     2(a).Full Adder.
     2(b). Half Adder.
3.6-bit Adder
     3(a).Full Adder.
     3(b). Half Adder.

So if you are visiting first time to my page them once have a look on the above codes also.Then you can have better understanding.

The Block Diagram of 4-Bit Vedic Multiplier

Code for 4-bit Vedic Multiplier is shown Below:-

----------------------------------------------------------------------------------

-- Company: VHDL Language

-- Engineer: Manohar Mohanta

-- 

-- Create Date:    20:16:31 12/25/2016 

-- Design Name:  Vedic Multiplier

-- Module Name:    Vedic_Multiplier_4bit - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Vedic_Multiplier_4bit is

    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);

           b : in  STD_LOGIC_VECTOR (3 downto 0);

           c : out  STD_LOGIC_VECTOR (7 downto 0));

end Vedic_Multiplier_4bit;

architecture Behavioral of Vedic_Multiplier_4bit is

signal s1 :STD_LOGIC_Vector (3 downto 0);signal s2 :STD_LOGIC_Vector (3 downto 0);

signal s3 :STD_LOGIC_Vector (3 downto 0);signal s4 :STD_LOGIC_Vector (3 downto 0);

signal s5 :STD_LOGIC_Vector (4 downto 0);signal s6 :STD_LOGIC_Vector (5 downto 0);

signal s7 :STD_LOGIC_Vector (3 downto 0);signal s8 :STD_LOGIC_Vector (5 downto 0);

signal s9 :STD_LOGIC_Vector (5 downto 0);signal s10 :STD_LOGIC_Vector (5 downto 0);

begin

Vedic_Multiplier_2bit_1:entity work.Vedic_Multiplier_2bits

port map( a =>a(1 downto 0),b =>b(1 downto 0),c=>s1);

Vedic_Multiplier_2bit_2:entity work.Vedic_Multiplier_2bits

port map( a =>a(3 downto 2),b =>b(1 downto 0),c=>s2);

Vedic_Multiplier_2bit_3:entity work.Vedic_Multiplier_2bits

port map( a =>a(1 downto 0),b =>b(3 downto 2),c=>s3);

Vedic_Multiplier_2bit_4:entity work.Vedic_Multiplier_2bits

port map( a =>a(3 downto 2),b =>b(3 downto 2),c=>s4);

c(1 downto 0)<= s1( 1 downto 0);

s7<=("00"&s1(3 downto 2));

Adder_4bit:entity work.Adder_4bit

port map(a=>s2,b=>s7,c=>s5(3 downto 0),cout=>s5(4));

s8<=("00"&s3(3 downto 0));s9<=(s4(3 downto 0)&"00");

Adder_6bit:entity work.Adder_6bit

port map(a=>s8,b=>s9,s=>s6);

s10<=('0'&s5);

Adder_6bit_1:entity work.Adder_6bit

port map(a=>s10,b=>s6,s=>c(7 downto 2));

end Behavioral;

Below is the Video Explaining The Concept:-

• Twitter
• Facebook
• Google
• Tumblr
• Pinterest