VHDL Implementation and Coding of Full Adder

To implement Half adder we have to know about the basic gates.There are only three gates used in this logic they are and gate ,xor gate and or gate.

The basic gate level diagram of Full adder is show below

VHDL Code for Full Adder 

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-- Company: VHDL Language

-- Engineer: Manohar Mohanta

-- 

-- Create Date:    11:14:06 11/27/2016 

-- Design Name:  Half Adder

-- Module Name:    ha - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity fa is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           s : out  STD_LOGIC;
           cout : out  STD_LOGIC);
end fa;

architecture Behavioral of fa is

begin
s <= ( a xor b) xor cin;
cout <= (a and b) or (( a xor b)and cin);
end Behavioral;

Below is the Video Explaining The Concept

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