VHDL Implementation and Coding of Half Adder

To implement Half adder we have to know about the basic gates.There are only two gates used in this logic they are and gate and xor gate.

The basic gate level diagram of Half adder is show below

VHDL Code for Half Adder 

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-- Company: VHDL Language

-- Engineer: Manohar Mohanta

-- 

-- Create Date:    11:14:06 11/27/2016 

-- Design Name:  Half Adder

-- Module Name:    ha - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ha is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           s : out  STD_LOGIC;

           c : out  STD_LOGIC);

end ha;

architecture Behavioral of ha is

begin

s <= a xor b;

c <= a and b;

end Behavioral;

Below is the Video Explaining The Concept

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